In the EEPROM memories, the logic value of a logic datum, or bit, stored in a memory cell is represented by an off or on state of the memory cell and more precisely by the value of the threshold voltage of a floating-gate transistor called the state transistor.
The on or off states of a memory cell may be modified at will in a write cycle generally comprising an erasing operation followed by a programming operation, implementing high write voltages.
FIG. 1 shows a cross-sectional view of a conventional EEPROM memory cell CEL0 and FIG. 2 shows a circuit diagram of such a memory cell CEL0.
Conventionally, memory cells are arranged in matrix arrays of rows (in the X direction) and columns (in the Y direction) in a memory plane PM.
The memory cell CEL0 includes a floating-gate transistor TE0, called the state transistor, and an access or selection transistor TA0 that is connected in series between the drain D of the state transistor TE0 and a bit line BL extending in the Y direction of the columns of the memory plane.
A tunnel injection zone INJT is conventionally formed on drain side of the state transistor TE0, above an implanted zone CAP currently designated by the term “capa implant” in the art.
The “capa implant” zone is especially intended to distance the tunnel injection zone INJT from the drain-channel junction of the state transistor.
The tunnel injection zone INJT includes a tunnel oxide OXTN that is thinner than a high-voltage gate oxide OXHV covering the channel of the state transistor TE0.
The source S of the state transistor TE0 is connected to a source line SL extending in the X direction of the rows of the memory plane, orthogonally to the Y direction.
An erase is carried out by applying a high positive voltage, for example 14 V, to the control gate CG0 of a state transistor TE0 and a for example zero voltage to its drain D, in order to inject electrical charges from the drain D into the floating gate FG via the Fowler-Nordheim effect.
The conventional programming operation aims, for its part, to apply selective stimuli to selected memory cells in order to place them in an on state.
Programming is carried out by applying a zero voltage to the control gate CG0 of the state transistor TE0 and a high positive voltage, for example 13 V, to its drain D, in order to extract the electric charges from the floating gate FG to the drain D, also by the Fowler-Nordheim effect.
The high positive voltage is transmitted from the bit line BL to the drain D via the selection transistor TA0, which is turned on by a voltage, for example 16 V, applied to its gate.
The usual approach used up to now with the aim of meeting the continual need to decrease the size of memory cells without degrading their endurance and data-retention performance and their performance in terms of parasitic signals has reached a technological limit.
Specifically, the decrease in the size of a memory cell is limited in the column direction, especially for the following reasons: since the selection transistor is a high-voltage transistor, decreasing its length runs the risk of causing leakage in the off state and/or of decreasing its maximum operating voltage; decreasing the length of the state transistor runs the risk of causing leakage in the off state and therefore of penalizing read-out; and decreasing the tunnel injection area would decrease the endurance of the cell.
Furthermore, decreasing the overrun of the “capa implant” zone would bring the tunnel injection zone closer to the drain-channel junction of the state transistor, and would run the risk of causing “band-to-band” leakage, resulting in an increase in programming current and increasing endurance.
Furthermore, the decrease in the size of a memory cell is also limited in the row direction, especially because of the influence of the state of the memory plane on the behavior of a memory cell (for example, the influence of neighboring memory cells or cells belonging to the same bit line). Such an influence is usually designated by those skilled in the art by the term “disturbance” or “disturb.”
A programming disturbance may manifest itself as a gradual variation in the charge on an unaddressed memory cell, i.e., unaddressed in the parasitic programming sense of the term.
During read-out, a disturbance may take the form of a disruption of the on/off state of a cell observed by the read-out amplifiers.
Decreasing coupling factor may lead to a decrease in the variation in the threshold voltage between the erased and programmed states.
An approach called the split-voltage approach has previously allowed these limits to be overcome while preserving the basic architecture of an EEPROM memory cell.
For example, during programming operations, the voltage on the control gate is no longer 0 V but −7 V and the voltage on the drain of the state transistor is no longer 13 V but 6 V.
However, the split-voltage approach is also reaching a limit as regards decreasing size without adversely affecting performance, especially because of the conventional memory-cell architecture employed in this approach.